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SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure

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dc.contributor.author Hassan, Hasan
dc.contributor.author Vijaykumar, Nandita
dc.contributor.author Khan, Samira
dc.contributor.author Ghose, Saugata
dc.contributor.author Chang, Kevin
dc.contributor.author Pekhimenko, Gennady
dc.contributor.author Lee, Donghyuk
dc.contributor.author Ergin, Oğuz
dc.contributor.author Mutlu, Onur
dc.date.accessioned 2019-06-26T07:40:34Z
dc.date.available 2019-06-26T07:40:34Z
dc.date.issued 2018-07
dc.identifier.citation Hassan, H., Vijaykumar, N., Khan, S., Ghose, S., Chang, K., Pekhimenko, G., ... & Mutlu, O. (2018). SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure. arXiv preprint arXiv:1805.03195. en_US
dc.identifier.issn 1820-4503
dc.identifier.uri http://hdl.handle.net/20.500.11851/1149
dc.description.abstract This paper summarizes the SoftMC DRAM characterization infrastructure, which was published in HPCA 2017 [44], and examines the work's significance and future potential. DRAM is the primary technology used for main memory in modern systems. Unfortunately, as DRAM scales down to smaller technology nodes, it faces key challenges in both data integrity and latency, which strongly affect overall system reliability and performance. To develop reliable and high-performance DRAM-based main memory in future systems, it is critical to characterize, understand, and analyze various aspects (e.g., reliability, latency) of modern DRAM chips. To enable this, there is a strong need for a publicly-available DRAM testing infrastructure that can flexibly and efficiently test DRAM chips in a manner accessible to both software and hardware developers. This work develops the first such infrastructure, SoftMC (Soft Memory Controller), an FPGA-based testing platform that can control and test memory modules designed for the commonly-used DDR (Double Data Rate) interface. SoftMC has two key properties: (i) it provides flexibility to thoroughly control memory behavior or to implement a wide range of mechanisms using DDR commands; and (ii) it is easy to use as it provides a simple and intuitive high-level programming interface for users, completely hiding the low-level details of the FPGA. We demonstrate the capability, flexibility, and programming ease of SoftMC with two example use cases. First, we implement a test that characterizes the retention time of DRAM cells. Experimental results we obtain using SoftMC are consistent with the findings of prior studies on retention time in modern DRAM, which serves as a validation of our infrastructure. Second, we validate two recently-proposed mechanisms, which rely on accessing recently-refreshed or recently-accessed DRAM cells faster than other DRAM cells. Using our infrastructure, we show that the expected latency reduction effect of these mechanisms is not observable in existing DRAM chips, which demonstrates the usefulness of SoftMC in testing new ideas on existing memory modules. Various versions of the SoftMC platform have enabled many of our other DRAM characterization studies [26, 29, 60, 61, 62, 68, 80, 84, 88, 117]. We discuss several other use cases of SoftMC, including the ability to characterize emerging non-volatile memory modules that obey the DDR standard. We hope that our open-source release of SoftMC fills a gap in the space of publicly-available experimental memory testing infrastructures and inspires new studies, ideas, and methodologies in memory system design. en_US
dc.language.iso eng en_US
dc.publisher IPSI Belgrade ltd. en_US
dc.rights info:eu-repo/semantics/closedAccess
dc.subject Dynamic random access storage en_US
dc.subject Data storage equipment en_US
dc.subject row buffer en_US
dc.title SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure en_US
dc.type article en_US
dc.relation.journal IPSI Bgd Transactions On internet Research en_US
dc.contributor.department TOBB ETU, Faculty of Engineering, Department of Computer Engineering en_US
dc.contributor.department TOBB ETÜ, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümü tr_TR
dc.identifier.volume 14
dc.identifier.issue 2
dc.contributor.orcid https://orcid.org/0000-0003-2701-3787
dc.identifier.wos WOS:000458407800006
dc.contributor.tobbetuauthor Ergin, Oğuz
dc.contributor.YOKid 143001
dc.contributor.wosresearcherID E-5717-2010
dc.contributor.ScopusAuthorID 6603141208
dc.relation.publicationcategory Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı tr_TR
dc.relation.other Google; Intel; NVIDIA; Samsung; VMware; NSF [1212962, 1320531, 1409723]; Intel Science and Technology Center for Cloud Computing; Semiconductor Research Corporation en_US


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