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  •   University of Economics & Technology Repository
  • Akademik Arşiv / Institutional Repository
  • Mühendislik Fakültesi / Faculty of Engineering
  • Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
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ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality

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Date
2016
Author
Hassan, Hasan
Pekhimenko, Gennady
Vijaykumar, Nandita
Seshadri, Vivek
Lee, Donghyuk
Ergin, Oğuz
Mutlu, Onur
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Abstract
DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism, called ChargeCache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core systems.
URI
https://ieeexplore.ieee.org/document/7446096
http://hdl.handle.net/20.500.11851/1979
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  • Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering

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