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ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality

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dc.contributor.author Hassan, Hasan
dc.contributor.author Pekhimenko, Gennady
dc.contributor.author Vijaykumar, Nandita
dc.contributor.author Seshadri, Vivek
dc.contributor.author Lee, Donghyuk
dc.contributor.author Ergin, Oğuz
dc.contributor.author Mutlu, Onur
dc.date.accessioned 2019-07-10T14:42:43Z
dc.date.available 2019-07-10T14:42:43Z
dc.date.issued 2016
dc.identifier.citation Hassan, H., Pekhimenko, G., Vijaykumar, N., Seshadri, V., Lee, D., Ergin, O., & Mutlu, O. (2016, March). ChargeCache: Reducing DRAM latency by exploiting row access locality. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) (pp. 581-593). IEEE. en_US
dc.identifier.isbn 978-1-4673-9211-2
dc.identifier.issn 1530-0897
dc.identifier.uri https://ieeexplore.ieee.org/document/7446096
dc.identifier.uri http://hdl.handle.net/20.500.11851/1979
dc.description 22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA) (2016 : Barcelona, SPAIN)
dc.description.abstract DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism, called ChargeCache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core systems. en_US
dc.language.iso eng en_US
dc.publisher IEEE en_US
dc.relation.ispartof International Symposium on High-Performance Computer Architecture-Proceedings
dc.rights info:eu-repo/semantics/closedAccess
dc.subject Dynamic random access storage en_US
dc.subject Data storage equipment en_US
dc.subject Refresh operations en_US
dc.title ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality en_US
dc.type conferenceObject en_US
dc.contributor.department TOBB ETU, Faculty of Engineering, Department of Computer Engineering en_US
dc.contributor.department TOBB ETÜ, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümü tr_TR
dc.identifier.startpage 581
dc.identifier.endpage 593
dc.contributor.orcid https://orcid.org/0000-0003-2701-3787
dc.identifier.wos WOS:000381808200048
dc.identifier.scopus 2-s2.0-84965013529
dc.contributor.tobbetuauthor Ergin, Oğuz
dc.contributor.YOKid 143001
dc.identifier.doi 10.1109/HPCA.2016.7446096
dc.contributor.wosresearcherID E-5717-2010
dc.contributor.ScopusAuthorID 6603141208
dc.relation.publicationcategory Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı tr_TR


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